1. Field
Various features relate to physically unclonable functions (PUFs), and in particular to PUFs based on the initial logic states of an array of magnetoresistive random-access memory (MRAM) cells.
2. Background
An on-chip PUF is a chip-unique challenge-response mechanism exploiting manufacturing process variations inside integrated circuits (ICs). When a physical stimulus (i.e., challenge) is applied to the PUF, the PUF generates a response in an unpredictable but repeatable way due to the complex interaction of the stimulus with the physical microstructure of the device employing the PUF. This exact microstructure depends on physical factors introduced during manufacture of the device employing the PUF, which are unpredictable. The PUF's “unclonability” means that each device employing the PUF has a unique and unpredictable way of mapping challenges to responses, even if one device is manufactured with the same process as another seemingly identical device. Thus, it is practically infeasible to construct a PUF with the same challenge-response behavior as another device's PUF because exact control over the manufacturing process is infeasible.
MRAM is a non-volatile random-access memory that, unlike conventional RAM, stores data not as electric charge but instead as electron spin within magnetic storage elements. FIG. 1, comprising FIGS. 1A and 1B, illustrates a schematic diagram of at least a portion of a spin transfer torque (STT) MRAM circuit cell 100 found in the prior art. The MRAM cell 100 shown in FIGS. 1A and 1B is an example of an “in-plane” STT MRAM cell. The MRAM cell 100 includes a free layer 102, a reference layer (also known as “pinned reference layer”) 104, a tunnel junction layer 106, and an anti-ferromagnetic (AFM) pinning layer 108. The free layer 102 is a ferromagnetic layer whose magnetic polarity is not fixed but is instead free to change direction in response to an external magnetic field (not shown). The reference layer 104 includes a first ferromagnetic layer 105 and a second ferromagnetic layer 107 that have opposite magnetic polarities. By contrast to the free layer 102, the reference layer 104 has a magnetic polarity that is fixed such that the magnetic polarities of the first and second ferromagnetic layers 105, 107 do not change direction in the presence of the aforementioned external magnetic field. The AFM pinning layer 108 is an anti-ferromagnetic layer that controls the magnetic polarities of the reference layer 106.
Situated in between the free layer 102 and the reference layer's first ferromagnetic layer 104 is the tunnel junction layer 106. The tunnel junction layer 106 is made of a very thin insulating material, such as magnesium oxide (MgO). The tunnel junction layer 106 is so thin that electrons may actually flow through (e.g., tunnel through) the layer 106 despite the layer 106 being an insulator. The magnetic polarity direction of the free layer 102 relative to the first ferromagnetic layer 105 (e.g., parallel to each other or antiparallel to each other) represents one of two different logical data bit states (e.g. data bit “1” or data bit “0”). In the example illustrated in FIG. 1A, the parallel orientation is shown with the free layer 102 having a magnetic polarity direction that is the same as the magnetic polarity direction of the first ferromagnetic layer 105. By contrast, FIG. 1B illustrates the antiparallel orientation with the free layer 102 having a magnetic polarity direction that is the opposite of the magnetic polarity direction of the first ferromagnetic layer 105.
A signal line voltage VSL applied to the MRAM cell 100 controls the flow of current ISL through the MRAM cell 100. For example, applying a voltage VSL that exceeds the transition voltage VT of the cell 100 causes the current ISL to flow in the direction shown in FIG. 1A and also causes the magnetic polarity of the free layer 102 to change direction into a parallel orientation. That is, the magnetic polarity direction of the free layer 102 is parallel to the magnetic polarity of the first ferromagnetic layer 105. To change the magnetic polarity direction of the free layer 102 back to an antiparallel orientation, a signal line voltage VSL that exceeds VT is applied in the orientation shown in FIG. 1B to cause the current ISL to flow in the opposite direction. In one example, the parallel state may be considered the first logical state representing a data bit “0,” and the antiparallel state may be considered the second logical state representing a data bit “1.”
FIG. 2 shows a top perspective schematic view of a portion of the in-plane MRAM cell 100 found in the prior art that is undergoing a manufacturing process step. During manufacture of the cell 100, an annealing process step is performed that initializes all of the MRAM cells 100 in the MRAM cell array (array not shown) to a first logical state, e.g., state “1.” Specifically, an external magnetic field along the MRAM cell's “easy axis” is applied during the annealing process step to initialize the MRAM cells 100 of the array. The “easy axis” is the preferred/relaxed direction of an MRAM cell free layer's magnetic polarity. For example, the easy axis of the in-plane MRAM cell 100 shown in FIG. 2 is the free layer's 102 long axis 203, which is parallel to the x-axis labeled in FIG. 2. Application of the annealing process step in the presence of the external magnetic field causes all of the MRAM cells 100 in the array to have a homogenous state (e.g., all in the first logical “1” state) prior to any logical state transition (as described with reference to FIGS. 1A and 1B) that may occur during typical use.
FIG. 3 shows a top perspective schematic view of a portion of a perpendicular MRAM cell 300 found in the prior art. Like the in-plane MRAM cell 100 shown in FIGS. 1A and 1B, the perpendicular MRAM cell 300 of FIG. 3 includes a free layer 302 and a reference layer 304. The relative orientation (parallel or antiparallel) of the magnetic polarity of the free layer 302 with respect to the reference layer 304 dictates the logical state (e.g., logical “0” or “1”) of the MRAM cell 300. The magnetic polarities of the perpendicular MRAM cell's 300 free layer 302 and reference layer 304 are typically oriented along a direction parallel to its perpendicular axis 303 (e.g., parallel to the y-axis shown in FIG. 3). The perpendicular MRAM cell 300 shown is similarly undergoing an annealing process that initializes the MRAM cell 300 (and all other MRAM cells in the array (array not shown)) to a first logical state, e.g., state “1.” An external magnetic field is applied during the annealing process step along the MRAM cell's 300 easy axis to initialize the MRAM cells 300 of the array. In the example shown in FIG. 3, the easy axis of the perpendicular MRAM cell 300 is the perpendicular axis 303, which is parallel to the y-axis shown in FIG. 3. Application of the annealing process step in the presence of the external magnetic field causes all of the MRAM cells 300 in the array to have a homogenous state (e.g., all in the first logical “1” state) prior to any logical state transition (as described with reference to FIGS. 1A and 1B) that may occur during typical use.
There exists a need for methods and apparatuses that implement PUFs based on MRAM cells. Specifically, there exists a need to provide methods and apparatuses that may implement PUFs based on the initial logic states of MRAM cell arrays. Such MRAM based PUFs may provide a secure means to uniquely identify electronic devices, such as integrated circuits, and/or provide secure cryptographic keys for cryptographic security algorithms.